Solder spheres (solder balls) Diameter Range (0.035-0.889mm), Solder ingots, Cyclomax(High TC) QSAC Series(High TC), Ecolloy (Low cost)
Sn-Ag-Cu (217~229 ℃)
Sn-Ag-Cu-Ni-Ge (217~229 ℃)
Sn-Bi Series- Sn58Bi (139℃)
Sn-Sb Series- Sn5Sb (245℃)
Sn-Pb Series- 63Sn-37Pb (183℃)
Solder spheres (solder balls) Diameter Range (0.035-0.889mm), Solder ingots, Cyclomax(High TC) QSAC Series(High TC), Ecolloy (Low cost)
Sn-Ag-Cu (217~229 ℃)
Sn-Ag-Cu-Ni-Ge (217~229 ℃)
Sn-Bi Series- Sn58Bi (139℃)
Sn-Sb Series- Sn5Sb (245℃)
Sn-Pb Series- 63Sn-37Pb (183℃)
State of the art Probe Cards, Production LED Equipment, Advanced Semiconductor Test Equipments: Manual Probe station, Semi-Automatic, Automated, High Power probe station RF & MW.
Comprehensive portfolio of automated wafer/device test, measurement, and inspection solutions for Mini LED, MicroLED, Laser Diode, Photodiode, LED and more
State of the art Probe Cards, Production LED Equipment, Advanced Semiconductor Test Equipments: Manual Probe station, Semi-Automatic, Automated, High Power probe station RF & MW.
Comprehensive portfolio of automated wafer/device test, measurement, and inspection solutions for Mini LED, MicroLED, Laser Diode, Photodiode, LED and more
Plasma Clean, Photoresist Strip/Clean/Descum, HMDS Vapor Prime/Image Reversal, Silane Monolayer Deposition, Polyimide/BCB/PBO/Low Temp Polymer Cure, Self Assembled Materials (SAM) Silane/HMDS Prime before PR, Polyimide/BCB/Other polymer cure
Plasma Clean, Photoresist Strip/Clean/Descum, HMDS Vapor Prime/Image Reversal, Silane Monolayer Deposition, Polyimide/BCB/PBO/Low Temp Polymer Cure, Self Assembled Materials (SAM) Silane/HMDS Prime before PR, Polyimide/BCB/Other polymer cure
Wafer Level Packaging (WLP) is combining wafer manufacturing and device encapsulation technologies. WLP is a chip-scale-packaging technology where many IC’s can be stacked together using suitable interconnect processes (like TSV or metal bumps) followed by encapsulation.
A combination of visible and infrared illumination for multiple quality assessment tasks, CD control, Undercut measurement, Residues inspection.
Wafer Level Packaging (WLP) is combining wafer manufacturing and device encapsulation technologies. WLP is a chip-scale-packaging technology where many IC’s can be stacked together using suitable interconnect processes (like TSV or metal bumps) followed by encapsulation.
A combination of visible and infrared illumination for multiple quality assessment tasks, CD control, Undercut measurement, Residues inspection.
Dicing Solutions (6”, 8”, 12” dicing saw) Dicing Blades, Chucks Dicing and back grinding tapes Mounting handling/blade dressing Dicing blade tools, Automatic washing and drying station, Wafer mounter
Dicing Solutions (6”, 8”, 12” dicing saw)
Dicing Blades, Chucks Dicing and back grinding tapes Mounting handling/blade dressing Dicing blade tools, Automatic washing and drying station, Wafer mounter
RF Reliability Burn-In System, HTOL / HAST Burn-In System, Automated Test Equipment (ATE), Yield Enhancement Metrology Tool, Parametric (WAT) Probe Card, Vertical Probe Card, MEMS VPC / CPC Probe Card,Test Socket & Contactor, Probe Station, µLED / VCSEL Integrated Test System, SiPH Test System, Power Device Analytical Tester, TMS / RMS / SPT Intelligent Test Operating System,Load board / Burn-In Board Substrates / PIB / PCI, WAT & Reliability Probe Card
Mask Aligner ideal for Microelectronics, LED / HB LED, 3D IC, SIOP, WLP, 2.5D Interposer, MEMS, BioMEMS, MicroFluidics, Compound Semi, Solar (HCPV), and Optoelectronics applications.
